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Verilog Code

Draw the timing waveforms for the two code fragments below. The waveforms should show how the values of signal a, b and f change with time, assumming that clk rises at time 0.
Code 1:
always@(posedge clk) begin
a = 1;
b = 0;
f = 0;
#1 f = a;
#2 f = b;
end
Code 2:
always@(posedge clk) begin
a = 1;
b = 0;
f = 0;
#1 f <= a; #2 f <= b; end